ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 80
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST7MC1xx/ST7MC2xx
16-BIT TIMER (Cont’d)
10.3.3.3 Input Capture
In this section, the index, i, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAPi pin (see figure 5).
ICiR register is a read-only register.
The active transition is software programmable
through the IEDGi bit of Control Registers (CRi).
Timing resolution is one count of the free running
counter: (
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC[1:0]) (see
– Select the edge of the active transition on the
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
– Select the edge of the active transition on the
80/309
1
Clock Control
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).
input capture coming from either the ICAP1 pin
or the ICAP2 pin
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input).
ICiR
f
CPU
/
CC[1:0]).
Bits).
MS Byte
ICiHR
LS Byte
ICiLR
Table 16
When an input capture occurs:
– ICFi bit is set.
– The ICiR register contains the value of the free
– A timer interrupt is generated if the ICIE bit is set
Clearing the Input Capture interrupt request (i.e.
clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
Notes:
1. After reading the ICiHR register, transfer of
2. The ICiR register contains the free running
3. The 2 input capture functions can be used
4. In One pulse Mode and PWM mode only the
5. The alternate inputs (ICAP1 & ICAP2) are
6. The TOF bit can be used with interrupt in order
running counter on the active transition on the
ICAPi pin (see
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
input capture data is inhibited and ICFi will
never be set until the ICiLR register is also
read.
counter value which corresponds to the most
recent input capture.
together even if the timer also uses the 2 output
compare functions.
input capture 2 can be used.
always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
Moreover if one of the ICAPi pin is configured
as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion i is disabled by reading the ICiHR (see note
1).
to measure event that go beyond the timer
range (FFFFh).
Figure
49).
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