ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 126
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
10.5.9.4 LIN Error Detection
LIN Header Error Flag
The LIN Header Error Flag indicates that an invalid
LIN Header has been detected.
When a LIN Header Error occurs:
– The LHE flag is set
– An interrupt is generated if the RIE bit is set and
If autosynchronization is enabled (LASE bit = 1),
this can mean that the LIN Synch Field is corrupt-
ed, and that the SCI is in a blocked state (LSF bit is
set). The only way to recover is to reset the LSF bit
and then to clear the LHE bit.
– The LHE bit is reset by an access to the SCISR
LHE/OVR Error Conditions
When Auto Resynchronization is disabled (LASE
bit = 0), the LHE flag detects:
– That the received LIN Synch Field is not equal to
– That an overrun occurred (as in standard SCI
– Furthermore, if LHDM is set it also detects that a
When the LIN auto-resynchronization is enabled
(LASE bit = 1), the LHE flag detects:
– That the deviation error on the Synch Field is
– A LIN Header Reception Timeout occurred.
– An overflow during the Synch Field Measure-
– That an overrun occurred on Fields other than
Deviation Error on the Synch Field
The deviation error is checking by comparing the
current baud rate (relative to the slave oscillator)
with the received LIN Synch Field (relative to the
master oscillator). Two checks are performed in
parallel:
– The first check is based on a measurement be-
126/309
1
the I[1:0] bits are cleared in the CCR register.
register followed by a read of the SCIDR register.
55h.
mode)
LIN Header Reception Timeout occurred (only if
LHDM is set).
outside the LIN specification which allows up to
+/-15.5% of period deviation between the slave
and master oscillators.
If T
set. Refer to
ment, which leads to an overflow of the divider
registers. If LHE is set due to this error then the
SCI goes into a blocked state (LSF bit is set).
the Synch Field (as in standard SCI mode)
tween the first falling edge and the last falling
HEADER
> T
Figure
HEADER_MAX
67. (only if LHDM is set to 1)
then the LHE flag is
– The second check is based on the measurement
When LHE is set due to this error then the SCI
goes into a blocked state (LSF bit is set).
LIN Header Time-out Error
When the LIN Identifier Field Detection Method is
used (by configuring LHDM to 1) or when LIN
auto-resynchronization is enabled (LASE bit = 1),
the
T
If the entire Header (up to and including the STOP
bit of the LIN Identifier Field) is not received within
the maximum time limit of 57 bit times then a LIN
Header Error is signalled and the LHE bit is set in
the SCISR register.
Figure 67. LIN Header Reception Timeout
The time-out counter is enabled at each break de-
tection. It is stopped in the following conditions:
- A LIN Identifier Field has been received
- An LHE error occurred (other than a timeout er-
ror).
- A software reset of LSF bit (transition from high to
low) occurred during the analysis of the LIN Synch
Field or
If LHE bit is set due to this error during the LIN
Synchr Field (if LASE bit = 1) then the SCI goes
into a blocked state (LSF bit is set).
HEADER_MAX
edge of the Synch Field. Let us refer to this peri-
od deviation as D:
of each bit time between both edges of the Synch
Field: this checks that each of these bit times is
large enough compared to the bit time of the cur-
rent baud rate.
be either set or reset depending on the dephas-
ing between the signal on the RDI line and the
CPU clock.
If the LHE flag is set, it means that:
D > 15.625%
If LHE flag is not set, it means that:
D < 16.40625%
If 15.625% ≤ D < 16.40625%, then the flag can
LIN Synch
Break
LINSCI
condition given by the LIN protocol.
automatically
LIN Synch
Field
T
HEADER
Identifier
Field
monitors
the
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