ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 60
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST7MC1xx/ST7MC2xx
10 ON-CHIP PERIPHERALS
10.1 WINDOW WATCHDOG (WWDG)
10.1.1 Introduction
The Window Watchdog is used to detect the oc-
currence of a software fault, usually generated by
external interference or by unforeseen logical con-
ditions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the contents of the downcounter before the T6
bit becomes cleared. An MCU reset is also gener-
ated if the 7-bit downcounter value (in the control
register) is refreshed before the downcounter has
reached the window register value. This implies
that the counter must be refreshed in a limited win-
dow.
10.1.2 Main Features
■
■
Figure 34. Watchdog Block Diagram
60/309
1
Programmable free-running downcounter
Conditional reset
– Reset (if watchdog activated) when the down-
– Reset (if watchdog activated) if the downcoun-
counter value becomes less than 40h
RESET
f
OSC2
MCC/RTC
11
MSB
Write WDGCR
RTC COUNTER
12-BIT MCC
T6:0 > W6:0 CMP
comparator
DIV 64
= 1 when
6
5
LSB
WDGA
-
0
TB[1:0] bits
(MCCSR
Register)
W6
T6
W5
WATCHDOG WINDOW REGISTER (WDGWR)
T5
WATCHDOG CONTROL REGISTER (WDGCR)
■
■
10.1.3 Functional Description
The counter value stored in the WDGCR register
(bits T[6:0]), is decremented every 16384 f
cycles (approx.), and the length of the timeout pe-
riod can be programmed by the user in 64 incre-
ments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit downcounter (T[6:0] bits) rolls
over from 40h to 3Fh (T6 becomes cleared), it ini-
tiates a reset cycle pulling low the reset pin for typ-
ically 30μs. If the software reloads the counter
while the counter is greater than the value stored
in the window register, then a reset is generated.
6-BIT DOWNCOUNTER (CNT)
Hardware/Software
(selectable by option byte)
Optional
(configurable by option byte)
ter is reloaded outside the window (see
37)
W4
T4
WDG PRESCALER
DIV 4
W3
T3
reset
W2
T2
on
W1
T1
Watchdog
HALT
W0
T0
instruction
activation
Figure
OSC2
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