ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 107
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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10.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)
10.5.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The LIN-dedicated features support the LIN (Local
Interconnect Network) protocol for both master
and slave nodes.
This chapter is divided into SCI Mode and LIN
mode sections. For information on general SCI
communications, refer to the SCI mode section.
For LIN applications, refer to both the SCI mode
and LIN mode sections.
10.5.2 SCI Features
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Full duplex, asynchronous communications
NRZ standard format (Mark/Space)
Independently programmable transmit and
receive baud rates up to 500K baud
Programmable data word length (8 or 9 bits)
Receive buffer full, Transmit buffer empty and
End of Transmission flags
2 receiver wake-up modes:
– Address bit (MSB)
– Idle line
Muting function for multiprocessor configurations
Separate enable bits for Transmitter and
Receiver
Overrun, Noise and Frame error detection
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10.5.3 LIN Features
– LIN Master
– LIN Slave
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error
– Parity interrupt
– Transmits parity bit
– Checks parity of received data byte
– 13-bit LIN Synch Break generation
– Automatic Header Handling
– Automatic baud rate resynchronization based
– Automatic baud rate adjustment (at CPU fre-
– 11-bit LIN Synch Break detection capability
– LIN Parity check on the LIN Identifier Field
– LIN Error management
– LIN Header Timeout
– Hot plugging support
6 interrupt sources
Parity control:
Reduced power consumption mode
on recognition and measurement of the LIN
Synch Field (for LIN slave nodes)
quency precision)
(only in reception)
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