ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 239
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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10-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRMSB register.
0: Conversion is not complete
1: Conversion complete
Bit 6:5 = PRSC[1:0] ADC clock prescaler selection
These bits are set and cleared by software.
Bit 4 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 3:0 = CS[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
EOC PRSC1 PRSC0 ADON
7
Channel Pin*
4MHz
2MHz
1MHz
f
ADC
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
PRSC1
CH3
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CS3
CH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CS2
CH1
PRSC0
CS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
CH0
CS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DATA REGISTER (ADCDRMSB)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[9:2] MSB of Analog Converted Value
This register contains the MSB of the converted
analog value.
DATA REGISTER (ADCDRLSB)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
This register contains the LSB of the converted an-
alog value.
D9
7
7
0
D8
0
D7
0
D6
0
ST7MC1xx/ST7MC2xx
D5
0
D4
0
D3
D1
239/309
D2
D0
0
0
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