ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 184
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
Three kinds of interrupt can be generated in
Speed Sensor Mode, as summarized in
104:
– C interrupt, when a capture event occurs; this in-
– RPI/RMI interrupts occur when the ST[3:0] bits of
– S interrupt occurs when a Speed Error happens
These interrupts may be masked individually.
Note on Delay Manager Initialization in Speed
Figure 104. Prescaler auto-change example
184/309
1
C
terrupt shares resources (Mask bit and Flag) with
the Commutation event in Switched/Au-
toswitched Mode, as these modes are mutually
exclusive.
the MPSR register are changed, either automat-
ically or by hardware.
(i.e. a successful comparison between
[MTIM:MTIML] and [MDREG:FF]). This interrupt
has the same channel as the Emergency Stop in-
terrupt (MCES), as it also warns the user about
abnormal system operation. The respective Flag
bits have to be tested in the interrupt service rou-
tine to differentiate Speed Errors from Emergen-
cy Stop events.
RMI Ratio Decrement
RPI
Notes:
E
APTURE
C
S
VENTS
FAFFh
FFFFh
8000h
5500h
Events:
Capture
Speed Error
Ratio Increment
[MTIM:MTIML]
[MTIM:MTIML] Input Clock:
C
F
F
x
x
/ 2
(ST[3:0] = n)
(ST[3:0] = n+1)
S
RPI
Figure
C
Measurement Mode: In order to set-up the
[MTIM:MTIML] counter properly before any speed
measurement, the following procedure must be
applied:
– The peripheral clock must be disabled (resetting
– MTIM, MTIML must be reset and appropriate val-
Note on MTIML: The Least Significant Byte of the
counter (MTIML) is not used when working in Po-
sition Sensor or Sensorless Modes.
Debug option: a signal reflecting the capture
events may be output on a standard I/O port for de-
bugging purposes. Refer to
page 172
the CKE bit in the MCRA register) to allow write
access to ST[3:0], MTIM and MTIML (refer to
ble
ues must be written in the ST[3:0] prescaler
adapt to the frequency of the signal being meas-
ured and to allow speed measurement with suffi-
cient resolution.
41),
for more details.
C
RMI
C
C
section10.6.7.3 on
WORKING
U
RANGE
SUAL
Ta-
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