ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 218
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
PWM CONTROL REGISTER (MPCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = PMS: PWM Mode Selection.
0: Standard mode: bit b7 in the MCPxH register
1: “8-bit” mode: bit b7 (extension bit) in the MCPxH
Bit 6 = OVFU: Phase U 100% duty cycle Selec-
tion.
0: Duty cycle defined by MCPUH:MCPUL register.
1: Duty cycle set at 100% on phase U at next up-
Bit 5 = OVFV: Phase V 100% duty cycle Selection.
0: Duty cycle defined by MCPVH:MCPVL register.
1: Duty cycle set at 100% on phase V at next up-
218/309
PMS
represents the extension bit.
register is located in the MPCR register (OVFx
bits); the number of active bits in MCPxH and
MCPxL is decreased to b15:b8 instead of
b15:b3.
date event and maintained till the next one. This
bit is reset once transferred to the active register
on update event.
date event and maintained till the next one. This
bit is reset once transferred to the active register
on update event.
7
OVFU OVFV OVFW CMS PCP2
PCP1
PCP0
0
Bit 4 = OVFW: Phase W 100% duty cycle Selec-
tion.
0: Duty cycle defined by MCPWH:MCPWL regis-
1: Duty cycle set at 100% on phase W at next up-
Bit 3 = CMS: PWM Counter Mode Selection.
0: Edge-aligned mode
1: Center-aligned mode
Bits 2:0 = PCP[2:0] PWM counter prescaler value.
This value divides the F
N is PCP[2:0] value.
frequency of the PWM counter input clock.
Table 73. PWM clock prescaler
PCP2
ter.
date event and maintained till the next one. This
bit is reset once transferred to the active register
on update event.
0
0
0
0
1
1
1
1
PCP1
0
0
1
1
0
0
1
1
PCP0 PWM counter input clock
0
1
0
1
0
1
0
1
Table 73
mtc
frequency by N, where
shows the resulting
F
F
F
F
F
F
F
F
mtc
mtc
mtc
mtc
mtc
mtc
mtc
mtc
/2
/3
/4
/5
/6
/7
/8
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