ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 109
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
Figure 62. SCI Block Diagram (in Conventional Baud Rate Generator Mode)
TDO
RDI
TIE
SCICR2
TRANSMITTER
INTERRUPT
CONTROL
TCIE
CLOCK
f
CPU
Transmit Data Register (TDR)
SCI
TRANSMIT
CONTROL
RIE
Transmit Shift Register
Write
ILIE
/16
TE
RE
/PR
RWU
WAKE
UNIT
UP
R8
SBK
T8
CONVENTIONAL BAUD RATE GENERATOR
SCP1
Received Data Register (RDR)
SCID M
Read
SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
Receive Shift Register
TDRE TC RDRF IDLE
TRANSMITTER RATE
CONTROL
RECEIVER
WAKE
CONTROL
(DATA REGISTER) SCIDR
PCE
RECEIVER RATE
CONTROL
PS PIE
ST7MC1xx/ST7MC2xx
OR/
LHE
SCICR1
SCIBRR
NF
RECEIVER
FE
CLOCK
SCISR
PE
109/309
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