ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 41
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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INTERRUPTS (Cont’d)
Servicing Pending Interrupts
As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter-
mined by the following two-step process:
– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-
Figure 21
Figure 21. Priority Decision Process
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and MCES can be consid-
ered as having the highest software priority in the
decision process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TRAP) and the maskable type (external
or from internal peripherals).
Non-Maskable Sources
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure
registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit Halt
mode.
■
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ority then the interrupt with the highest hardware
priority is serviced first.
TRAP (Non Maskable Software Interrupt)
PRIORITY SERVICED
HIGHEST HARDWARE
20). After stacking the PC, X, A and CC
Same
describes this decision process.
INTERRUPTS
SOFTWARE
PENDING
PRIORITY
HIGHEST SOFTWARE
PRIORITY SERVICED
Different
ing to the flowchart in
level interrupt.
■
The RESET source has the highest priority in the
ST7. This means that the first current routine has
the highest software priority (level 3) and the high-
est hardware priority.
See the RESET chapter for more details.
Maskable Sources
Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pending.
■
This hardware interrupt occurs when a specific
edge is detected on the dedicated MCES pin or
when an error is detected by the micro in the motor
speed measurement. The interrupt request is
maintained as long as the MCES pin is low if the
interrupt is enabled by the EIM bit in the MIMR reg-
ister.
■
External interrupts allow the processor to exit from
Halt low power mode.
External interrupt sensitivity is software selectable
through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically ORed.
■
Usually the peripheral interrupts cause the MCU to
exit from Halt mode except those mentioned in the
“Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
RESET
MCES (MTC Emergency Stop)
External Interrupts
Peripheral Interrupts
Figure 20
ST7MC1xx/ST7MC2xx
as a MCES top
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