ST7MC2S6 STMicroelectronics, ST7MC2S6 Datasheet - Page 271
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ST7MC2S6
Manufacturer Part Number
ST7MC2S6
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet
1.ST7MC1K4.pdf
(309 pages)
Specifications of ST7MC2S6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 147. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
4. Depends on f
OSC
Symbol
1/t
t
t
t
t
su(SS)
w(SCKH)
w(SCKL)
t
t
t
h(SS)
t
dis(SO)
t
t
t
t
t
t
r(SCK)
f(SCK)
t
su(MI)
t
h(MO)
f
v(MO)
MISO
MOSI
su(SI)
a(SO)
v(SO)
h(SO)
h(MI)
c(SCK)
h(SI)
, and T
SCK
SS
1)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
1)
OUTPUT
INPUT
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
CPU
see note 2
. For example, if f
t
Parameter
a(SO)
t
su(SS)
t
su(SI)
4)
CPU
t
t
MSB IN
w(SCKH)
w(SCKL)
MSB OUT
=8MHz, then T
t
t
h(SI)
c(SCK)
Master
f
Slave
f
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
CPU
CPU
t
DD
v(SO)
=8MHz
=8MHz
DD
CPU
,
BIT6 OUT
Conditions
and 0.7xV
= 1/f
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
3)
CPU
DD
=125ns and t
BIT1 IN
.
t
h(SO)
(4 x T
su(SS)
f
t
t
CPU
r(SCK)
f(SCK)
0.0625
see I/O port pin description
Min
CPU
120
100
100
100
100
100
90
=550ns
0
0
0
0
/128
ST7MC1xx/ST7MC2xx
) + 50
LSB IN
LSB OUT
t
h(SS)
f
f
CPU
CPU
Max
120
240
120
120
2
4
/4
/2
t
dis(SO)
271/309
Unit
MHz
ns
note 2
see
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