ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 60

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

Power saving modes
9.4.1
Caution:
60/188
Active-halt mode
Active-halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when Active-halt mode is enabled.
The MCU can exit Active-halt mode on reception of a Lite timer/ AT timer interrupt or a reset.
●
●
When entering Active-halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wakeup time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
As soon as Active-halt is enabled, executing a HALT instruction while the watchdog is active
does not generate a reset if the WDGHALT bit is reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 27. Active-halt timing overview
1. This delay occurs only if the MCU exits Active-halt mode by means of a RESET.
When exiting Active-halt mode by means of a reset, a 256 CPU cycle delay occurs.
After the start up delay, the CPU resumes operation by fetching the reset vector which
woke it up (see
When exiting Active-halt mode by means of an interrupt, the CPU immediately resumes
operation by servicing the interrupt vector which woke it up (see
[Active-halt Enabled]
Figure
28).
Doc ID 13562 Rev 3
INSTRUCTION
RUN
HALT
ACTIVE
HALT
CYCLE DELAY
INTERRUPT
256 CPU
RESET
OR
1)
VECTOR
FETCH
RUN
Figure
28).
ST7LITE49M