ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 53

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

ST7LITE49M
8.5
8.5.1
8.5.2
Description of interrupt registers
CPU CC register interrupt bits
Reset value: 111x 1010(xAh)
Bits 5, 3 = I1, I0 Software interrupt priority bits
Table 15.
Interrupt software priority registers (ISPRx)
All ISPRx register bits are read/write except bit 7:4 of ISPR3 which are read only.
Reset value: 1111 1111 (FFh)
ISPRx registers contain the interrupt software priority of each interrupt vector. Each interrupt
vector (except RESET and TRAP) has corresponding bits in these registers to define its
software priority. This correspondence is shown in
Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0
bits in the CC register.
These two bits indicate the current interrupt software priority (see
These two bits are set/cleared by hardware when entering in interrupt. The loaded
value is given by the corresponding bits in the interrupt software priority registers
(ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see
TRAP and RESET events can interrupt a level 3 program.
7
1
ISPR0
ISPR1
ISPR2
ISPR3
Level 3 (= interrupt disable*)
Interrupt software priority
Setting the interrupt software priority
1
Level 0 (main)
I1_11
I1_3
I1_7
7
1
Level 1
Level 2
I1
I0_11
I0_3
I0_7
1
Doc ID 13562 Rev 3
Table 17: Dedicated interrupt instruction
I1_10
I1_2
I1_6
1
H
Read/write
I0_10
I0_2
I0_6
1
I0
Table
Level
High
Low
I1_1
I1_5
I1_9
16.
1
N
I0_1
I0_5
I0_9
1
I1
1
0
1
Table
Z
set).
I1_12
I1_0
I1_4
I1_8
15).
Interrupts
I0
0
1
0
1
I0_12
I0_0
I0_4
I0_8
C
0
53/188
0