ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 173

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ST7LITE49M

Manufacturer Part Number
ST7LITE49M
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7LITE49M

4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance
10k write/erase cycles guaranteed Data retention
128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
A/d Converter
10 input channels

Available stocks

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Quantity
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Part Number:
ST7LITE49M
Manufacturer:
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0
ST7LITE49M
14
14.1
14.1.1
Device configuration and ordering information
This device is available for production in user programmable version (Flash).
ST7LITE49M XFlash devices are shipped to customers with a default program memory
content (FFh).
Option bytes
The two option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes can be accessed only in programming mode (for example using a standard
ST7 programming tool).
Option byte 1
Bits 7:6 = CKSEL[1:0] Start-up clock selection.
Table 90.
Bits 5:4 = Reserved, must always be 1.
Bits 3:2 = LVD[1:0] Low voltage detection selection.
Table 91.
Bit 1 = WDG SW Hardware or software watchdog
Bit 0 = WDG HALT Watchdog reset on Halt
These bits are used to select the startup frequency. By default, the internal RC is
selected.
These option bits enable the low voltage detection block (LVD) with a selected
threshold as shown in
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Startup clock selection
LVD threshold configuration
External crystal/ceramic resonator
Internal RC as startup clock
AWU RC as a startup clock
Configuration
External clock
Medium voltage threshold
Highest voltage threshold
Lowest voltage threshold
LVD off (default value)
Table
Configuration
Doc ID 13562 Rev 3
91.
Device configuration and ordering information
CKSEL1
0
0
1
1
VD1
1
1
0
0
CKSEL0
0
1
0
1
VD0
173/188
1
0
1
0

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