ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 127

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

ST7LITE49M
11.5.4
11.5.5
Configuring the A/D conversion
The analog input ports must be configured as input, no pull-up, no interrupt (see
I/O
as a logic input.
To assign the analog channel to convert, select the CH[2:0] bits in the ADCCSR register.
Set the ADON bit to enable the A/D converter and to start the conversion. From this time on,
the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
●
●
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
To read the 10 bits, perform the following steps:
1.
2.
3.
To read only 8 bits, perform the following steps:
1.
2.
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
Low power modes
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Table 46.
Interrupts
None.
ports). Using these pins as analog inputs does not affect the ability of the port to be read
The EOC bit is set by hardware.
The result is in the ADCDR registers.
Poll the EOC bit
Read ADCDRL
Read ADCDRH. This clears EOC automatically.
Poll EOC bit
Read ADCDRH. This clears EOC automatically.
Mode
Wait
Halt
Effect of low power modes on the A/D converter
After wakeup from Halt mode, the A/D Converter requires a stabilization time
t
STAB
(see Electrical Characteristics) before accurate conversions can be
Doc ID 13562 Rev 3
No effect on A/D converter
A/D Converter disabled.
Description
performed.
On-chip peripherals
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