ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 39

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

ST7LITE49M
7.3.2
7.3.3
7.3.4
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Electrical Characteristics
section for more details.
A RESET signal originating from an external source must have a duration of at least
t
asynchronous and therefore the MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
Figure 15. Reset block diagram
1. See
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V
the minimum level specified for the selected f
A proper reset signal for a slow rising V
RC network connected to the RESET pin.
Internal low voltage detector (LVD) reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●
●
The device RESET pin acts as an output that is pulled low when V
(rising edge) or V
The LVD filters spikes on V
h(RSTL)in
RESET
Power-on reset
Voltage drop reset
Section 12.2.1: Illegal opcode reset on page 136
in order to be recognized (see
DD
lower than V
V
DD
R
ON
DD
larger than t
Doc ID 13562 Rev 3
IT-
Filter
(falling edge) as shown in
GENERATOR
DD
Figure 16: Reset
PULSE
g(VDD)
supply can generally be provided by an external
OSC
for more details on illegal opcode reset conditions.
to avoid parasitic resets.
frequency.
Supply, reset and clock management
sequences). This detection is
___
___
___
ILLEGAL OPCODE RESET
Figure 16.
LVD RESET
WATCHDOG RESET
DD
is lower than V
INTERNAL
RESET
ON
weak pull-up
DD
IT+
is over
1)
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