ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 54

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

Interrupts
Caution:
54/188
The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and
I0 bits of the CC register are both set.
Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is
kept (Example: previous = CFh, write = 64h, result = 44h).
Table 16.
1. Bits in the ISPRx registers can be read and written but they are not significant in the interrupt process
If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Table 17.
1. During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the
Instruction
POP CC
management.
current software priority up to the next IRET instruction or one of the previously mentioned instructions.
JRNM
TRAP
HALT
IRET
JRM
RIM
WFI
SIM
Interrupt vector vs. ISPRx bits
Dedicated interrupt instruction set
Disable interrupt (level 3 set)
Enable interrupt (level 0 set)
Jump if I1:0 = 11 (level 3)
Vector address
Interrupt routine return
Pop CC from the stack
FFFBh-FFFAh
FFE1h-FFE0h
FFF9h-FFF8h
Entering Halt mode
Jump if I1:0 <> 11
New description
Wait for interrupt
Software trap
...
Doc ID 13562 Rev 3
Load 10 in I1:0 of CC
Load 11 in I1:0 of CC
Function/example
Pop CC, A, X, PC
Software NMI
Mem => CC
I1:0 <> 11
I1:0 = 11
(1)
I1_13 and I0_13 bits
I1_0 and I0_0 bits
I1_1 and I0_1 bits
ISPRx bits
I1
I1
I1
1
1
1
1
1
...
H
H
H
I0
I0
I0
0
0
1
1
0
(1)
ST7LITE49M
N
N
N
Z
Z
Z
C
C
C