ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 43

• Manufacturer Part Number: ST7LITE49M
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49M

• 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10k write/erase cycles guaranteed Data retention
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
• A/d Converter: 10 input channels

ST7LITE49M
Note:
7.4.3
Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD
levels are not correlated. Refer to
143
Figure 19. Using the AVD to monitor V
Low power modes
Table 8.
Interrupts
The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Table 9.
AVDF bit
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
LVD RESET
V
V
V
V
IT+(AVD)
IT+(LVD)
IT-(LVD)
IT-(AVD)
for more details.
Mode
Wait
Halt
Interrupt event
V
Low power modes
Description of interrupt events
AVD event
DD
0
No effect on SI. AVD interrupts cause the device to exit from Wait mode.
The SICSR register is frozen.
The AVD remains active but the AVD interrupt cannot be used to exit from Halt
mode.
1
Doc ID 13562 Rev 3
INTERRUPT Cleared by
Section 13.3.2 on page 142
V
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
hyst
Event flag
reset
AVDF
DD
RESET
Description
Supply, reset and clock management
Control
Enable
AVDIE
bit
and
1
Exit from
Section 13.3.3 on page
Wait
Yes
INTERRUPT Cleared by
hardware
0
Exit from
Halt
No
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