ST7LITE49M STMicroelectronics, ST7LITE49M Datasheet - Page 44

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ST7LITE49M

Manufacturer Part Number
ST7LITE49M
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7LITE49M

4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance
10k write/erase cycles guaranteed Data retention
128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
A/d Converter
10 input channels

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7LITE49M
Manufacturer:
ST
0
Supply, reset and clock management
7.5
7.5.1
7.5.2
Note:
44/188
Register description
Main clock control/status register (MCCSR)
Reset value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main clock out enable bit
Bit 0 = SMS Slow mode selection bit
RC control register (RCCR)
Reset value: 1111 1111 (FFh)
Bits 7:0 = CR[9:2] RC oscillator frequency adjustment bits
To tune the oscillator, write a series of different values in the register until the correct
frequency is reached. The fastest method is to use a dichotomy starting with 80h.
CR9
This bit is read/write by software and cleared by hardware after a reset. This bit allows
to enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the input clock f
0: Normal mode (f
1: Slow mode (f
These bits must be written immediately after reset to adjust the RC oscillator frequency
and to obtain an accuracy of 1%. The application can store the correct value for each
voltage range in Flash memory and write it to this register at start-up.
00h = maximum available frequency
FFh = lowest available frequency
These bits are used with the CR[1:0] bits in the SICSR register. Refer to
7
0
7
CR8
0
OSC
CPU =
CPU =
or f
f
CR7
OSC
0
OSC
f
OSC
Doc ID 13562 Rev 3
/32)
/32.
CR6
0
Read/write
Read/write
CR5
0
CR4
0
MCO
CR3
Chapter
ST7LITE49M
CR2
SMS
0
0
7.5.3.

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