ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 306

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

Device configuration and ordering information
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Device configuration and ordering information
Introduction
Each device is available for production in user programmable versions (Flash) as well as in
factory coded versions (ROM/FASTROM).
ST72561-Auto devices are ROM versions. ST72P561-Auto devices are Factory Advanced
Service Technique ROM (FASTROM) versions: They are factory-programmed HDFlash
devices.
ST72F561-Auto Flash devices are shipped to customers with a default content (FFh), while
ROM factory coded parts contain the code supplied by the customer. This implies that Flash
devices have to be configured by the customer using the Option Bytes while the ROM
devices are factory-configured.
Flash devices
Flash configuration
The option bytes allows the hardware configuration of the microcontroller to be selected.
They have no address in the memory map and can be accessed only in programming mode
(for example using a standard ST7 programming tool). The default content of the Flash is
fixed to FFh. To program directly the Flash devices using ICP, Flash devices are shipped to
customers with a reserved internal clock source enabled. In masked ROM devices, the
option bytes are fixed in hardware by the ROM code (see option list).
Option byte 0
OPT7 = WDGHALT Watchdog reset on HALT
This option bit determines if a RESET is generated when entering HALT mode while the
Watchdog is active.
OPT6 = WDGSW Hardware or software watchdog
This option bit selects the watchdog type.
OPT5 = reserved, must be kept at default value.
OPT4 = LVD Voltage detection
This option bit enables the voltage detection block (LVD).
OPT3 = PLL OFF PLL activation
This option bit activates the PLL which allows multiplication by two of the main input clock
frequency. The PLL is guaranteed only with an input frequency between 2 and 4 MHz.
0: no reset generation when entering halt mode
1: reset generation when entering halt mode
0: hardware (watchdog always enabled)
1: software (watchdog to be enabled by software)
0: LVD on
1: LVD off
0: PLL x2 enabled
1: PLL x2 disabled
Doc ID 12370 Rev 8
ST72561-Auto