ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 132

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

8-bit timer (TIM8)
Note:
132/324
1
2
3
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OC
Timing resolution is one count of the free running counter: (f
Procedure
To use the output compare function, select the following in the CR2 register:
●
●
And select the following in the CR1 register:
●
●
When a match is found between OCRi register and CR register:
●
●
●
The OC
the following formula:
Where:
Δ
f
PRESC
Table
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1.
2.
Once the OCIE bit is set both output compare features may trigger interrupt requests. If only
one is needed in the application, the interrupt routine software needs to discard the
unwanted compare interrupt. This can be done by checking the OCF1 and OCF2 flags and
resetting them both.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
When the timer clock is f
OCiR register value (see
CPU
t
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
Select the timer clock (CC[1:0]) (see
Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
Set the OCIE bit to generate an interrupt if it is needed.
OCFi bit is set.
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).
A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
Reading the SR register while the OCFi bit is set.
An access (read or write) to the OCiR register.
55)
=
=
=
i
R register value required for a specific timing application can be calculated using
Output compare period (in seconds)
PLL output x2 clock frequency in hertz (or f
Timer prescaler factor (2, 4, 8 or 8000 depending on CC[1:0] bits, see
CPU
Figure
i
/2, OCFi and OCMPi are set while the counter value equals the
R value to 00h.
Doc ID 12370 Rev 8
66). This behavior is the same in OPM or PWM mode.
Δ
OCiR =
Table
Δt
PRESC
55).
*
f
CPU
OSC
CPU
/2 if PLL is not enabled)
/
CC[1:0]
).
ST72561-Auto