ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 208

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

LINSCI serial communication interface (LIN master only)
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software sequence (an access to the SCISR register followed by a read to the SCIDR
register).
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the
ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the
SCISR register followed by a read to the SCIDR register).
The IDLE bit is not be set again until the RDRF bit has been set itself (that is, a new idle line
occurs).
Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently being received in the shift register is
ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated if
RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the
SCISR register followed by a read to the SCIDR register).
When this bit is set, the RDR register content is not lost but the shift register is overwritten.
Bit 2 = NF Noise flag.
This bit is set by hardware when noise is detected on a received frame. It is cleared by a
software sequence (an access to the SCISR register followed by a read to the SCIDR
register).
This bit does not generate interrupt as it appears at the same time as the RDRF bit which
itself generates an interrupt.
Bit 1 = FE Framing error.
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by a software sequence (an access to the SCISR register followed
by a read to the SCIDR register).
This bit does not generate an interrupt as it appears at the same time as the RDRF bit which
itself generates an interrupt. If the word currently being transferred causes both frame error
and overrun error, it is transferred and only the OR bit is set.
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a
software sequence (a read to the status register followed by an access to the SCIDR data
register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: data is not received
1: received data is ready to be read
0: no idle line is detected
1: idle line is detected
0: no overrun error
1: overrun error is detected
0: no noise is detected
1: noise is detected
0: no framing error is detected
1: framing error or break character is detected
0: no parity error
1: parity error
Doc ID 12370 Rev 8
ST72561-Auto