ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 173

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
15.8.5
Note:
Contains the received or transmitted data character, depending on whether it is read from or
written to.
The data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see
The RDR register provides the parallel interface between the input shift register and the
internal bus (see
Baud rate register (SCIBRR)
Read/ write
Reset value: 0000 0000 (00h)
When LIN slave mode is disabled, the SCIBRR register controls the conventional baud rate
generator.
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges
Table 63.
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to
the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
Table 64.
SCP1
DR7
7
7
TR dividing factor
PR prescaler
Transmitter rate divider
SCP0
DR6
PR prescaling factor
Figure
Figure
1
2
4
8
77).
13
77).
1
3
4
SCT2
DR5
LINSCI serial communication interface (LIN master/slave)
Doc ID 12370 Rev 8
SCT1
DR4
SCT2
0
SCT0
DR3
SCP1
0
1
SCR2
DR2
SCT1
0
1
SCR1
DR1
SCP0
SCT0
0
1
0
1
0
1
0
1
SCR0
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DR0
0
0