ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 148

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

Serial peripheral interface (SPI)
14.3.3
Caution:
14.3.4
Note:
148/324
Note: The slave must have the same CPOL and CPHA settings as the master.
Note: MSTR and SPE bits remain set only if SS is high).
Figure 73. Hardware/software slave select management
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register
(by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1.
2.
3.
If the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not
taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
●
●
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Write to the SPICR register:
–
–
Write to the SPICSR register:
–
Write to the SPICR register:
–
The SPIF bit is set by hardware.
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
An access to the SPICSR register while the SPIF bit is set
A read to the SPIDR register
Select the clock frequency by configuring the SPR[2:0] bits.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 74
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
Set the MSTR and SPE bits
shows the four possible configurations.
SS external pin
Doc ID 12370 Rev 8
SSI bit
SSM bit
1
0
SS internal
ST72561-Auto