ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 171

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
Note:
15.8.3
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped and the end of the current
byte transfer in order to reduce power consumption.This bit is set and cleared by software.
Bit 4 = M Word length.
This bit determines the word length. It is set or cleared by software.
The M bit must not be modified during a data transfer (both transmission and reception).
Bit 3 = WAKE Wake-Up method.
This bit determines the SCI Wake-Up method, it is set or cleared by software.
If the LINE bit is set, the WAKE bit is deactivated and replaced by the LHDM bit.
Bit 2 = PCE Parity control enable.
This bit is set and cleared by software. It selects the hardware parity control (generation and
detection for byte parity, detection only for LIN parity).
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity will be selected after the current byte.
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hardware parity control when a parity error is
detected (PE bit set). The parity error involved can be a byte parity error (if bit PCE is set
and bit LPE is reset) or a LIN parity error (if bit PCE is set and bit LPE is set).
Control register 2 (SCICR2)
Read/ write
Reset value: 0000 0000 (00h)
1. This bit has a different function in LIN mode, please refer to the LIN mode register description.
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
TIE
0: SCI enabled
1: SCI prescaler and outputs disabled
0: 1 start bit, 8 data bits, 1 stop bit
1: 1 start bit, 9 data bits, 1 stop bit
0: idle line
1: address mark
0: parity control disabled
1: parity control enabled
0: even parity
1: odd parity
0: parity error interrupt disabled
1: parity error interrupt enabled
0: interrupt is inhibited
1: in SCI interrupt is generated whenever TDRE = 1 in the SCISR register
7
TCIE
RIE
LINSCI serial communication interface (LIN master/slave)
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