ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 112

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

16-bit timer
Note:
12.3.7
112/324
1
2
3
4
5
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OC
●
●
●
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
When the timer clock is f
OCiR register value (see
When the timer clock is f
while the counter value equals the OCiR register value (see
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OC
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
Forced compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both One Pulse mode and PWM mode.
Figure 54. Output compare block diagram
Write to the OCiHR register (further compares are inhibited).
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set).
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
16-bit
16 BIT FREE RUNNING
OC1R Register
OUTPUT COMPARE
16-bit
CIRCUIT
OC2R Register
COUNTER
16-bit
CPU
CPU
Figure
i
R register and the OLVi bit should be changed after each
/2, OCFi and OCMPi are set while the counter value equals the
/4, f
Doc ID 12370 Rev 8
CPU
OC1E
55). This behavior is the same in OPM or PWM mode.
OCIE
/8 or in external clock mode, OCFi and OCMPi are set
OC2E
OCF1
i
R register:
FOLV2 FOLV1
(Control Register 2) CR2
(Control Register 1) CR1
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
Figure
OLVL1
0
56).
Latch
Latch
1
2
ST72561-Auto
OCMP2
OCMP1
Pin
Pin