ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 220

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

beCAN controller (beCAN)
220/324
After the SLEEP bit has been cleared, Sleep mode is exited once beCAN has synchronized
with the CAN bus, refer to
cleared by hardware.
Test mode
Test mode can be selected by the SILM and LBKM bits in the CDGR register. These bits
must be configured while beCAN is in Initialization mode. Once test mode has been
selected, beCAN is started in Normal mode.
Silent mode
The beCAN can be put in Silent mode by setting the SILM bit in the CDGR register.
In Silent mode, the beCAN is able to receive valid data frames and valid remote frames, but
it sends only recessive bits on the CAN bus and it cannot start a transmission. If the beCAN
has to send a dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted
internally so that the CAN core monitors this dominant bit, although the CAN bus may
remain in recessive state. Silent mode can be used to analyze the traffic on a CAN bus
without affecting it by the transmission of dominant bits (acknowledge bits, error frames).
Figure 97. beCAN in silent mode
Loop back mode
The beCAN can be set in loop back mode by setting the LBKM bit in the CDGR register. In
loop back mode, the beCAN treats its own transmitted messages as received messages
and stores them (if they pass acceptance filtering) in the FIFO.
Figure 98. beCAN in loop back mode
This mode is provided for self-test functions. To be independent of external events, the CAN
core ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a data
Figure
Doc ID 12370 Rev 8
96. The sleep mode is exited once the SLAK bit has been
beCAN
beCAN
CANTX CANRX
CANTX CANRX
Tx
=1
Tx
Rx
Rx
ST72561-Auto