ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 99

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
Table 37.
Input capture 1 high register (IC1HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 1 event).
Input capture 1 low register (IC1LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 1 event).
Output compare 1 high register (OC1HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
IC1HR
IC1LR
OC1HR
MSB
MSB
MSB
R/W
1:0
Bit
R
R
7
7
7
3
2
CSR register description (continued)
Bit name
R/W
R
R
6
6
6
OCF2
TIMD
-
R/W
Output compare flag 2
Timer disable
Reserved, must be kept cleared
R
R
5
5
5
0: No match (reset value)
1: The content of the free running counter has matched the content
of the OC2R register. To clear this bit, first read the SR register, then
read or write the low byte of the OC2R (OC2LR) register.
This bit is set and cleared by software. When set, it freezes the timer
prescaler and counter and disables the output functions (OCMP1
and OCMP2 pins) to reduce power consumption. Access to the timer
registers is still available, allowing the timer configuration to be
changed, or the counter reset, while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
R/W
R
R
4
4
4
R/W
R
R
3
3
3
Function
R/W
R
R
2
2
2
Reset value: 1000 0000 (80h)
On-chip peripherals
Reset value: undefined
Reset value: undefined
R/W
R
R
1
1
1
R/W
LSB
LSB
LSB
R
R
0
0
0
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