ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 131

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
10.5.7
SCI registers
Status register (SCISR)
Table 47.
SCISR
TDRE
Bit
R
7
7
6
5
4
SCISR register description
Bit name
TC
R
6
TDRE
RDRF
IDLE
TC
RDRF
Transmit data register empty
Transmission complete
Received data ready flag
Idle line detect
R
5
This bit is set by hardware when the content of the TDR register has
been transferred into the shift register. An interrupt is generated if the
TIE bit = 1 in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data are not transferred to the shift register unless the TDRE
bit is cleared.
This bit is set by hardware when transmission of a frame containing
data is complete. An interrupt is generated if TCIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the
SCISR register followed by a write to the SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a preamble or a break.
This bit is set by hardware when the content of the RDR register has
been transferred to the SCIDR register. An interrupt is generated if
RIE = 1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR
register).
0: Data are not received
1: Received data are ready to be read
This bit is set by hardware when an idle line is detected. An interrupt
is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR register followed by a
read to the SCIDR register).
0: No idle line is detected
1: Idle line is detected
Note: The IDLE bit is not set again until the RDRF bit is set (i.e. a
new idle line occurs).
IDLE
R
4
OR
R
3
Function
NF
R
2
Reset value: 1100 0000 (C0h)
On-chip peripherals
FE
R
1
131/201
PE
R
0