ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 81

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
Note:
16-bit read sequence (from either the counter register or alternate counter register)
Figure 33. 16-bit read sequence
The user must read the MS byte first, then the LS byte value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS byte of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, one pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
●
●
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1.
2.
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by wait mode.
In halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a reset).
The TOF bit of the SR register is set
A timer interrupt is generated if the TOIE bit of the CR1 register is set and the I bit of the
CC register is cleared
Reading the SR register while the TOF bit is set
An access (read or write) to the CLR register
Beginning of the sequence
Sequence completed
At t0 +∆t
At t0
Read MS byte
Read LS byte
instructions
Other
Returns buffered LS byte
LS byte is buffered
value at t0
On-chip peripherals
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