ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 92

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
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Pulse width modulation mode
Pulse width modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse width modulation mode uses the complete output compare 1 function plus the OC2R
register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use pulse width modulation mode:
1.
2.
3.
4.
Figure 45. Pulse width modulation cycle
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.
Load the OC2R register with the value corresponding to the period of the signal using
the appropriate formula below according to the timer clock source used
Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1 = 0 and OLVL2 = 1) using the appropriate formula below according to the timer
clock source used
Select the following in the CR1 register:
–
–
Select the following in the CR2 register:
–
–
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register
Set OC1E bit (the OCMP1 pin is then dedicated to the output compare 1 function)
Set the PWM bit
Select the timer clock (CC[1:0]) (see
counter = OC2R
counter = OC1R
When
When
Pulse width modulation cycle
Counter is reset to FFFCh
Table 36: CR2 register
OCMP1 = OLVL2
OCMP1 = OLVL1
ICF1 bit is set
description)
ST7232Axx-Auto