ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 79

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
10.3.3
Caution:
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The block diagram is shown in
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
Counter register (CR)
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Alternate counter register (ACR)
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These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
status register, (SR), (see
counter register) on page
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and PWM
mode.
The timer clock depends on the clock control bits (bits 3 and 2) of the CR2 register, as
illustrated in
every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The
timer frequency can be f
In Flash devices, Timer A functionality has the following restrictions:
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a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pinout
description. When reading an input signal on a non-bonded pin, the value is always ‘1’.
Reduced power mode
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)
Counter high register (CHR) is the most significant byte (MS byte)
Counter low register (CLR) is the least significant byte (LS byte)
Alternate counter high register (ACHR) is the most significant byte (MS byte)
Alternate counter low register (ACLR) is the least significant byte (LS byte)
TAOC2HR and TAOC2LR registers are write only
Input capture 2 is not implemented
The corresponding interrupts cannot be used (ICF2, OCF2 forced by hardware to zero)
Table 36: CR2 register
CPU
16-bit read sequence (from either the counter register or alternate
81).
/2, f
Figure
CPU
/4, f
description. The value in the counter register repeats
32.
CPU
/8 or an external frequency.
On-chip peripherals
(a)
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