ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 112

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
10.4.6
Note:
Caution:
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Figure 52. Single master/multiple slave configuration
Low power modes
Table 39.
Using the SPI to wakeup the MCU from halt mode
In slave configuration, the SPI is able to wakeup the ST7 device from halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
When waking up from halt mode, if the SPI remains in slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from halt mode state to normal
state. If the SPI exits from slave mode, it returns to normal state immediately.
The SPI can wake up the ST7 from halt mode only if the slave select signal (external SS pin
or the SSI bit in the SPICSR register) is low when the ST7 enters halt mode. So if slave
selection is configured as external (see
the master drives a low level on the SS pin when the slave enters halt mode.
Wait
Halt
5V
Mode
SS
SCK
SCK
Effect of low power modes on SPI
MOSI
MOSI
Slave MCU
Master
MCU
No effect on SPI.
SPI interrupt events cause the device to exit from wait mode.
SPI registers are frozen.
In halt mode, the SPI is inactive. SPI operation resumes when the MCU is
woken up by an interrupt with ‘exit from halt mode’ capability. The data received
is subsequently read from the SPIDR register when the software is running
(interrupt vector fetching). If several data are received before the wake up event,
then an overrun error is generated. This error can be detected after the fetch of
the interrupt routine that woke up the device.
MISO
MISO
SS
SCK
MOSI
Slave MCU
Slave select management on page
MISO
SS
Description
SCK
MOSI
Slave MCU
MISO
SS
SCK
ST7232Axx-Auto
MOSI
105), make sure
Slave MCU
MISO
SS