SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 649

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6462B–ATARM–6-Sep-11
6462B–ATARM–6-Sep-11
Equation 1
Table 38-13. Minimum LCDDOTCK Period in LCDC Core Clock Cycles (Continued)
The LCDDEN signal indicates valid data in the LCD Interface.
After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to
cause the line to be displayed on the panel.
The following timing parameters can be configured:
There is a limitation in the minimum values of VHDLY, HPW and HBP parameters imposed by
the initial latency of the datapath. The total delay in LCDC clock cycles must be higher than or
equal to the latency column in
formula:
where:
The LCDVSYNC is asserted once per frame. This signal is asserted to cause the LCD's line
pointer to start over at the top of the display. The timing of this signal depends on the type of
LCD: STN or TFT LCD.
In STN mode, the high phase corresponds to the complete first line of the frame. In STN mode,
this signal is synchronized with the first active LCDDOTCK rising edge in a line.
In TFT mode, the high phase of this signal starts at the beginning of the first line. The following
timing parameters can be selected:
DISTYPE
STN Color
STN Color
STN Color
• Vertical to Horizontal Delay (VHDLY): The delay between the falling edge of LCDVSYNC and
• Horizontal Pulse Width (HPW): The LCDHSYNC pulse width is configurable in HPW field of
• Horizontal Back Porch (HBP): The delay between the LCDHSYNC falling edge and the first
• Horizontal Front Porch (HFP): The delay between end of valid data and the generation of the
• VHDLY, HPW, HBP are the value of the fields of LCDTIM1 and LCDTIM2 registers
• PCLK_PERIOD is the period of LCDDOTCK signal measured in LCDC Clock cycles
• DPATH_LATENCY is the datapath latency of the configuration, given in
• Vertical Pulse Width (VPW): LCDVSYNC pulse width is configurable in VPW field of the
the generation of LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register.
The delay is equal to (VHDLY+1) LCDDOTCK cycles.
LCDTIM2 register. The width is equal to (HPW + 1) LCDDOTCK cycles.
LCDDOTCK rising edge with valid data at the LCD Interface is configurable in the HBP field
of the LCDTIM2 register. The delay is equal to (HBP+1) LCDDOTCK cycles.
next LCDHSYNC is configurable in the HFP field of the LCDTIM2 register. The delay is equal
to (HFP+VHDLY+2) LCDDOTCK cycles.
644
LCDTIM1 register. The pulse width is equal to (VPW+1) lines.
(
VHDLY
SCAN
Single
Dual
Dual
+
HPW
Configuration
Table 38-4 on page
+
HBP
+
3
)
×
PCLK_PERIOD
IFWIDTH
8
8
16
644. This limitation is given by the following
≥
DPATH_LATENCY
LCDDOTCK Period
2
4
6
Table 38-4 on page
SAM9G10
SAM9G10
651
651