SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 645

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6462B–ATARM–6-Sep-11
6462B–ATARM–6-Sep-11
registers (DP_i) and considers not only the pixel gray level number, but also its horizontal
coordinate.
Table 38-10
Table 38-10. Dithering Duty Cycle
The duty cycles for gray levels 0 and 15 are 0 and 1, respectively.
The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7
and 6/7). The dithering pattern for the first pair member is the inversion of the one for the
second.
The DP_i registers contain a series of 4-bit patterns. The (3-m)
pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be
turned on or off in the current frame. The operation is shown by the examples below.
Consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3,
respectively. The four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register
used is DP3_5 =”1010 0101 1010 0101 1111”.
Gray Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
shows the correspondences between the gray levels and the duty cycle.
Duty Cycle
1
6/7
4/5
3/4
5/7
2/3
3/5
4/7
1/2
3/7
2/5
1/3
1/4
1/5
1/7
0
Pattern Register
-
DP6_7
DP4_5
DP3_4
DP5_7
DP2_3
DP3_5
DP4_7
~DP1_2
~DP4_7
~DP3_5
~DP2_3
~DP3_4
~DP4_5
~DP6_7
-
th
bit of the pattern determines if a
SAM9G10
SAM9G10
647
647