SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 34

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SAM9G10

Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G10

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
10.10 Synchronous Serial Controller
10.11 Timer Counter
10.12 MultiMediaCard Interface
34
SAM9G10
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
• IrDA modulation and demodulation
• Test Modes
• Provides serial synchronous communication links used in audio and telecom applications
• Contains an independent receiver and transmitter and a common clock divider.
• Offers a configurable frame sync and data length.
• Receiver and transmitter can be programmed to start automatically or on detection of
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
• Three 16-bit Timer Counter Channels
• Wide range of functions including:
• Each channel is user-configurable and contains:
• Two global registers that act on all three TC Channels
• Two double-channel MultiMediaCard Interfaces, allowing concurrent transfers with 2 cards
• Compatibility with MultiMediaCard Specification Version 3.31
• Compatibility with SD Memory Card Specification Version 1.0
• Compatibility with SDIO Specification Version V1.1
• Cards clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
(with CODECs in Master or Slave Modes, I
more).
different event on the frame sync signal.
signal.
– NACK handling, error counter with repetition and iteration limit
– Communication at up to 115.2 Kbps
– Remote Loopback, Local Loopback, Automatic Echo
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
2
S, TDM Buses, Magnetic Card Reader and
6462B–ATARM–6-Sep-11

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