SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 86
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.6.3
13.6.4
86
SAM3U Series
Fault status registers and fault address registers
Lockup
Usually, the exception priority, together with the values of the exception mask registers, deter-
mines whether the processor enters the fault handler, and whether a fault handler can preempt
another fault handler. as described in
In some situations, a fault with configurable priority is treated as a hard fault. This is called prior-
ity escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. This means that if a corrupted stack causes a fault, the fault handler
executes even though the stack push for the handler failed. The fault handler operates but the
stack contents are corrupted.
Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused
the fault, as shown in
Table 13-12. Fault status and fault address registers
The processor enters a lockup state if a hard fault occurs when executing the hard fault han-
dlers. When the processor is in lockup state it does not execute any instructions. The processor
remains in lockup state until:
Handler
Hard fault
Memory
management fault
Bus fault
Usage fault
• A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is
• An exception handler causes a fault for which the priority is the same as or lower than the
• A fault occurs and the handler for that fault is not enabled.
• it is reset
fault occurs because a fault handler cannot preempt itself because it must have the same
priority as the current priority level.
because the handler for the new fault cannot preempt the currently executing fault handler.
currently executing exception.
Status register
name
HFSR
MMFSR
BFSR
UFSR
Table
13-12.
“Exception model” on page
Address register
name
-
MMFAR
BFAR
-
Register description
“Hard Fault Status Register” on page
201
“Memory Management Fault Status
Register” on page 196
“Memory Management Fault Address
Register” on page 202
“Bus Fault Status Register” on page 197
“Bus Fault Address Register” on page
203
“Usage Fault Status Register” on page
199
77.
6430E–ATARM–29-Aug-11
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