SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 823
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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37.8.5
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
WRITE_SINGLE_BLOCK Operation using DMA Controller
1. Wait until the current command execution has successfully terminated.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Program HSMCI_DMA register with the following fields:
5. Issue a WRITE_SINGLE_BLOCK command writing HSMCI_ARG then HSMCI_CMDR.
6. Program the DMA Controller.
c. Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR
– OFFSET field with dma_offset.
– CHKSIZE is user defined and set according to DMAC_DCSIZE.
– DMAEN is set to true to enable DMA hardware handshaking in the HSMCI. This bit
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMAC transfer by
c. Program the channel registers.
d. The DMAC_SADDRx register for channel x must be set to the location of the
e. The DMAC_DADDRx register for channel x must be set with the starting address of
f.
g. Program DMAC_CTRLBx register for channel x with the following field’s values:
h. Program DMAC_CFGx register for channel x with the following field’s values:
was previously set to false.
reading the DMAC_EBCISR register.
source data. When the first data location is not word aligned, the two LSB bits
define the temporary value called dma_offset. The two LSB bits of
DMAC_SADDRx must be set to 0.
the HSMCI_FIFO address.
Program DMAC_CTRLAx register of channel x with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–DCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with CEILING((block_length + dma_offset) / 4), where
–DST_INCR is set to INCR, the block_length value must not be larger than the
–SRC_INCR is set to INCR.
–FC field is programmed with memory to peripheral flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
–FIFOCFG defines the watermark of the DMAC channel FIFO.
–DST_H2SEL is set to true to enable hardware handshaking on the destination.
–DST_PER is programmed with the hardware handshaking ID of the targeted
the ceiling function is the function that returns the smallest integer not less than
x.
HSMCI_FIFO aperture.
DMA controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
SAM3U Series
SAM3U Series
823
823
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