SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 516
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Figure 30-5. Input Glitch Filter Timing
Figure 30-6. Input Debouncing Filter Timing
30.5.10
516
516
Divided Slow Clock
if PIO_IFSR = 0
if PIO_IFSR = 1
PIO_PDSR
PIO_PDSR
Pin Level
SAM3U Series
SAM3U Series
if PIO_IFSR = 0
if PIO_IFSR = 1
Input Edge/Level Interrupt
PIO_PDSR
PIO_PDSR
Pin Level
MCK
up to 2 cycles Tmck
not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to
be visible it must exceed 1 Selected Clock cycle, whereas for a glitch to be reliably filtered out,
its duration must not exceed 1/2 Selected Clock cycle.
The filters also introduce some latencies, this is illustrated in
The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs
on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt
detection. The glitch and debouncing filters require that the PIO Controller clock is enabled.
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a
level on an I/O line. The Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt
Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and dis-
able the input change interrupt by setting and clearing the corresponding bit in PIO_IMR
(Interrupt Mask Register). As Input change detection is possible only by comparing two succes-
1 cycle
1 cycle
up to 2 cycles Tmck
PIO_IFCSR = 1
PIO_IFCSR = 0
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 1.5 cycles
1 cycle
up to 2.5 cycles
up to 2 cycles Tmck
2 cycles
Figure 30-5
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 2 cycles
and
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
1 cycle
1 cycle
Figure
up to 2 cycles Tmck
30-6.
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