SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 66
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.3.4
13.3.5
13.3.6
66
SAM3U Series
Exceptions and interrupts
Data types
The Cortex Microcontroller Software Interface Standard
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the
Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception
changes the normal flow of software control. The processor uses handler mode to handle all
exceptions except for reset. See
84
The NVIC registers control interrupt handling. See
page 165
The processor:
For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface Standard
(CMSIS) defines:
The CMSIS includes address definitions and data structures for the core peripherals in the Cor-
tex-M3 processor. It also includes optional interfaces for middleware components comprising a
TCP/IP stack and a Flash file system.
CMSIS simplifies software development by enabling the reuse of template code and the combi-
nation of CMSIS-compliant software components from various middleware vendors. Software
vendors can expand the CMSIS to include their peripheral definitions and access functions for
those peripherals.
This document includes the register names defined by the CMSIS, and gives short descriptions
of the CMSIS functions that address the processor core and the core peripherals.
from the architectural short names that might be used in other documents.
The following sections give more information about the CMSIS:
This document uses the register short names defined by the CMSIS. In a few cases these differ
• supports the following data types:
• supports 64-bit data transfer instructions.
• manages all data memory accesses as little-endian. Instruction memory and Private
• a common way to:
• the names of:
• a device-independent interface for RTOS kernels, including a debug channel.
•
for more information.
Peripheral Bus (PPB) accesses are always little-endian. See
attributes” on page 68
“Power management programming hints” on page 88
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
– access peripheral registers
– define exception vectors
– the registers of the core peripherals
– the core exception vectors
for more information.
for more information.
“Exception entry” on page 83
“Nested Vectored Interrupt Controller” on
and
“Memory regions, types and
“Exception return” on page
6430E–ATARM–29-Aug-11
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