SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 626
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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32.8.11
Name:
Address:
Access:
• SPIWPVS: SPI Write Protection Violation Status
• SPIWPVSRC: SPI Write Protection Violation Source
This Field indicates the APB Offset of the register concerned by the violation (SPI_MR or SPI_CSRx)
626
626
31
23
15
–
–
7
–
SPIWPVS value
SAM3U Series
SAM3U Series
SPI Write Protection Status Register
0x1
0x2
0x3
0x4
0x5
0x6
0x7
30
22
14
SPI_WPSR
0x400080E8
Read-only
–
–
6
–
The Write Protection has blocked a Write access to a protected register (since the last read).
Software Reset has been performed while Write Protection was enabled (since the last read or
since the last write access on SPI_MR, SPI_IER, SPI_IDR or SPI_CSRx).
Both Write Protection violation and software reset with Write Protection enabled have occurred
since the last read.
Write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi
(while the Chip Select “i” was active) since the last read.
The Write Protection has blocked a Write access to a protected register and write accesses have
been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while the Chip Select
“i” was active) since the last read.
Software Reset has been performed while Write Protection was enabled (since the last read or
since the last write access on SPI_MR, SPI_IER, SPI_IDR or SPI_CSRx) and some write
accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi (while
the Chip Select “i” was active) since the last read.
- The Write Protection has blocked a Write access to a protected register.
and
- Software Reset has been performed while Write Protection was enabled.
and
- Write accesses have been detected on SPI_MR (while a chip select was active) or on SPI_CSRi
(while the Chip Select “i” was active) since the last read.
29
21
13
–
–
5
–
28
20
12
–
–
4
–
SPIWPVSRC
27
19
11
–
–
3
–
Violation Type
26
18
10
–
–
2
SPIWPVS
25
17
–
–
9
1
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
24
16
–
–
8
0
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