SAM3U4E Atmel Corporation, SAM3U4E Datasheet - Page 825
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SAM3U4E
Manufacturer Part Number
SAM3U4E
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U4E
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
57
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
5
Twi (i2c)
2
Uart
5
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
50
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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37.8.6.2
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)
In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to
use only WORD AHB access. When the block length is no longer a multiple of 4 this is no longer
true. The DMA controller is programmed to copy exactly the block length number of bytes using
2 transfer descriptors.
8. Wait for XFRDONE in HSMCI_SR register.
1. Use the previous step until READ_SINGLE_BLOCK then
2. Program the DMA controller to use a two descriptors linked list.
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMA transfer by
c. Program the channel registers in the Memory for the first descriptor. This descriptor
d. The LLI_W.DMAC_SADDRx field in memory must be set with the starting address
e. The LLI_W.DMAC_DADDRx field in the memory must be word aligned.
f.
g. Program LLI_W.DMAC_CTRLBx with the following field’s values:
h. Program LLI_W.DMAC_CFGx register for channel x with the following field’s
i.
–Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and
reading the DMAC_EBCISR register.
will be word oriented. This descriptor is referred to as LLI_W, standing for LLI word
oriented transfer.
of the HSMCI_FIFO address.
Program LLI_W.DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to zero. (descriptor fetch is enabled for the SRC)
–DST_DSCR is set to one. (descriptor fetch is disabled for the DST)
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA
values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero meaning that address are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
Program LLI_W.DMAC_DSCRx with the address of LLI_B descriptor. And set
DSCRx_IF to the AHB Layer ID. This operation actually links the Word oriented
waiting for request.
skipped later.
controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
SAM3U Series
SAM3U Series
825
825
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