ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 423

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.6.3
32.6.4
8331A–AVR–07/11
Repeat Counter Register
Operand Count Register
addressing is based on an address already stored in the pointer register prior to the access
itself. Indirect data access can be optionally combined with pointer register post-increment. The
indirect access mode has an option that makes it possible to load or read the pointer register
without accessing any other registers. Any register update is performed in a little-endian fashion.
Hence, loading a single byte of the address register will always update the LSB byte while the
MSB bytes are left unchanged.
The pointer register is not involved in addressing registers in the PDI control and status register
space (CSRS space).
The REPEAT instruction is always accompanied by one or more operand bytes that define the
number of times the next instruction should be repeated. These operand bytes are copied into
the repeat counter register upon reception. During the repeated executions of the instruction
immediately following the REPEAT instruction and its operands, the repeat counter register is
decremented until it reaches zero, indicating that all repetitions have completed. The repeat
counter is also involved in key reception.
Immediately after an instruction (except the LDCS and STCS instructions) a specified number of
operands or data bytes (given by the size parts of the instruction) are expected. The operand
count register is used to keep track of how many bytes have been transferred.
Atmel AVR XMEGA AU
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