ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 17

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.14.9
8331A–AVR–07/11
SREG – Status Register
The status register (SREG) contains information about the result of the most recently executed
arithmetic or logic instruction.
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set for interrupts to be enabled. If the global interrupt
enable register is cleared, none of the interrupts are enabled independent of the individual inter-
rupt enable settings. This bit is not cleared by hardware after an interrupt has occurred. This bit
can be set and cleared by the application with the SEI and CLI instructions, as described in
“Instruction Set Description.” Changing the I flag through the I/O-register result in a one-cycle
wait state on the access.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions bit load (BLD) and bit store (BST) use the T bit as source or destination
for the operated bit. A bit from a register in the register file can be copied into this bit by the BST
instruction, and this bit can be copied into a bit in a register in the register file by the BLD
instruction.
• Bit 5 – H: Half Carry Flag
The half carry flag (H) indicates a half carry in some arithmetic operations. Half carry Is useful in
BCD arithmetic. See “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
The sign bit is always an exclusive or between the negative flag, N, and the two’s complement
overflow flag, V. See “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag (V) supports two’s complement arithmetic. See “Instruction
Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The negative flag (N) indicates a negative result in an arithmetic or logic operation. See “Instruc-
tion Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The zero flag (Z) indicates a zero result in an arithmetic or logic operation. See “Instruction Set
Description” for detailed information.
• Bit 0 – C: Carry Flag
The carry flag (C) indicates a carry in an arithmetic or logic operation. See “Instruction Set
Description” for detailed information.
Bit
+0x0F
Read/Write
Initial Value
R/W
7
0
I
R/W
T
6
0
⊕
V
R/W
H
5
0
R/W
S
4
0
Atmel AVR XMEGA AU
R/W
3
V
0
R/W
2
N
0
R/W
Z
1
0
R/W
C
0
0
SREG
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