ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 388

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.10.6
29.10.6.1
29.10.6.2
8331A–AVR–07/11
CH0DATAH – Channel 0 Data Register High
Right-adjusted
Left-adjusted
• Bit 1 – CH1DRE: Channel 1 Data Register Empty
This bit indicates that the data register for channel 1 is empty, meaning that a new conversion
value may be written. If the bit is cleared, writing to the data register can cause a conversion
value to be lost. This bit is directly used for DMA Request.
• Bit 0 – CH0DRE: Channel 0 Data register Empty
This bit indicates that the data register for channel 0 is empty, meaning that a new conversion
value may be written. If the bit is cleared, writing to the data register can cause a conversion
value to be lost.This bit is directly used for DMA Request.
The two registers CHnDATAH and CHnDATAL are the high byte and low byte respectively of the
12-bit value CHnDATA that is converted to a voltage on DAC channel n. By default, the 12 bits
are distributed with 8 bits in CHnDATAL and 4 bits in 4 LSB position of CHnDATAH (right-
adjusted).To select left-adjusted data set the LEFTADJ bit in the CTRLC register.
When left adjusted data is selected, it is possible to do 8-bit conversions by only writing to the
high byte of CHnDATA, i.e., CHnDATAH. The TEMP register should be initialized to zero if only
8-bit conversion mode is used.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:0 – CHDATA[11:8]: Conversion Data Register Channel 0, 4MSB
These bits are the 4 MSB of the 12-bit value to convert to channel 0 in right-adjusted mode.
• Bit 7:0 – CHDATA[11:4]: Conversion Data Register Channel 0, 8MSB
These bits are the 8 MSB of the 12-bit value to convert to channel 0 in left-adjusted mode.
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Bit
+0x19
Read/Write
Read/Write
Initial Value
Initial Value
7
R/W
R
–
0
0
6
R/W
R
–
0
0
5
R/W
R
–
0
0
Atmel AVR XMEGA AU
4
R/W
–
R
0
0
CHDATA[11:4]
3
R/W
R/W
0
0
2
R/W
R/W
0
0
CHDATA[11:8]
1
R/W
R/W
0
0
0
R/W
R/W
0
0
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