ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 283

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.11 Register Summary - TWI
21.12 Register Summary - TWI Master
21.13 Register Summary - TWI Slave
21.14 Interrupt Vector Summary
Table 21-10. TWI interrupt vectors and their word offset addresses.
8331A–AVR–07/11
Address
Address
Address
+0x00
+0x01
+0x08
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
+0x06
+0x00
+0x01
+0x02
+0x03
+0x04
+0x05
Offset
0x00
0x02
Name
Name
Name
ADDRMASK
MASTER
STATUS
STATUS
CTRLC
SLAVE
CTRLA
CTRLB
CTRLA
CTRLB
BAUD
ADDR
ADDR
CTRL
DATA
DATA
Source
SLAVE_vect
MASTER_vect
Bit 7
Bit 7
Bit 7
RIF
DIF
–
–
–
–
INTLVL[1:0]
INTLVL[1:0]
Bit 6
Bit 6
Bit 6
APIF
WIF
–
–
–
–
Interrupt Description
TWI slave interrupt vector
TWI master interrupt vector
CLKHOLD
CLKHOLD
Bit 5
Bit 5
Bit 5
RIEN
DIEN
–
–
–
–
ADDRMASK[7:1]
Offset address for TWI Master
Offset address for TWI Slave
RXACK
RXACK
Bit 4
Bit 4
Bit 4
APIEN
WIEN
–
–
–
–
ADDR[7:0]
ADDR[7:0]
BAUD[7:0]
DATA[7:0]
DATA[7:0]
ARBLOST
ENABLE
ENABLE
Bit 3
Bit 3
Bit 3
COLL
–
–
–
TIMEOUT[1:0]
Atmel AVR XMEGA AU
BUSERR
BUSERR
ACKACT
ACKACT
Bit 2
Bit 2
Bit 2
PIEN
–
–
SDAHOLD
TPMEN
Bit 1
Bit 1
Bit 1
QCEN
DIR
–
BUSSTATE[1:0]
CMD[1:0]
CMD[1:0]
ADDREN
Bit 0
EDIEN
Bit 0
SMEN
Bit 0
SMEN
AP
–
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