ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 242

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.10 Interrupts and Events
8331A–AVR–07/11
Figure 20-10. Transfer Complete FIFO
To manage the FIFO, a 5-bit write pointer (FIFOWP) and 5-bit read pointer (FIFORP) is used by
the USB module and application software, respectively. FIFORP and FIFOWP are one's com-
plemented, thus hold negative values. The SRAM location of the data is the sum of the EPPTR
and the read or write pointer. The number of items in the FIFO is the difference between the
FIFOWP and the FIFORP. For the programmer, FIFORP and FIFOWP values have to be cast
to a signed 8-bit integer and deduct the offset into the FIFO from this signed integer.
The Transaction Complete Interrupt Flag (TRNIF) in the INFLAGSB[CLR,SET] register is set to
indicate an non-empty FIFO when FIFORP != FIFOWP, and cleared when they are equal, and
also set when the FIFO is full.
Each time an endpoint IN or OUT transaction completes successfully, its endpoint configuration
table address is stored in the FIFO at the current write pointer position (i.e. EPPTR +
2*FIFOWP) and FIFOWP is decremented. When the pointer reaches the FIFO size, it wraps to
zero. When application software reads the FIFORP, this is decremented in the same way. Read-
ing the write pointer has no effect. The endpoint configuration table address can then be read
directly from (EPPTR + 2*FIFORP).
Figure 20-11. USB Transaction Complete FIFO example
The USB module can generate interrupts and events. The module has 10 interrupt sources.
These are split between two interrupt vectors, the transaction complete (TRNCOMPL) interrupt
and the bus event (BUSEVENT) interrupt. An interrupt group is enabled by setting its interrupt
level (INTLVL), while different interrupt sources are enabled individually or in groups.
FIFOWP
4x( MAXEP +1)
EPPTR –
ADDRESS
SRAM
EPPTR
FIFO
FIFOWP
FIFORP
FIFOWP
Ep X
USB_ TC_ FIFO
INTERNAL SRAM
ENDPOINT DESCRIPTOR TABLE
FIFO
X
FIFORP
FIFOWP
TC_ EP_ ADDRH _ MAX
EpY
TC_ EP_ ADDRH_2
TC_ EP_ ADDRH_2
TC_EP_ ADDRL_1
TC_ EP_ ADDRH_1
TC_EP_ ADDRL_0
TC _ EP _ ADDRH_0
Atmel AVR XMEGA AU
FIFO
X
Y
FIFORP
FIFOWP
FIFOWP
Ep Z
FIFO
Y
Y
X
X
Z
Z
FIFORP
t
FIFORP
FIFORP
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