ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 276

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.9.6
21.9.7
8331A–AVR–07/11
ADDR
DATA
–
–
TWI Master Data Register
TWI Master Address Register
The baud rate (BAUD) register defines the relation between the system clock and the TWI bus
clock (SCL) frequency. The frequency relation can be expressed by using the following
equation:
The BAUD register must be set to a value that results in a TWI bus clock frequency (f
or less than 100kHz or 400kHz, depending on which standard the application should comply
with. The following equation [2] expresses equation [1] solved for the BAUD value:
The BAUD register should be written only while the master is disabled.
When the address (ADDR) register is written with a slave address and the R/W bit while the bus
is idle, a START condition is issued and the 7-bit slave address and the R/W bit are transmitted
on the bus. If the bus is already owned when ADDR is written, a repeated START is issued. If
the previous transaction was a master read and no acknowledge is sent yet, the acknowledge
action is sent before the repeated START condition.
After completing the operation and the acknowledge bit from the slave is received, the SCL line
is forced low if arbitration was not lost. WIF is set.
If the bus state is unknown when ADDR is written, WIF is set and BUSERR is set.
All TWI master flags are automatically cleared when ADDR is written. This includes BUSERR,
ARBLOST, RIF, and WIF. The master ADDR can be read at any time without interfering with
ongoing bus activity.
The data (DATA) register is used when transmitting and receiving data. During data transfer,
data are shifted from/to the DATA register and to/from the bus. This implies that the DATA regis-
ter cannot be accessed during byte transfers, and this is prevented by hardware. The DATA
f
TWMBR
TWI
Bit
+0x05
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
=
--------------------------------------- - [Hz]
2(5
=
+
------------- - 5
2f
f
TWMBR)
f
sys
TWI
sys
R/W
R/W
7
0
7
0
–
[2]
R/W
R/W
6
0
6
0
[1]
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
ADDR[7:0]
DATA[7:0]
R/W
R/W
Atmel AVR XMEGA AU
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
TWI
) equal
ADDR
DATA
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