ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 387

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.10.4
29.10.5
8331A–AVR–07/11
EVCTRL – Event Control Register
STATUS – Status Register
• Bit 0 - LEFTADJ: DAC Left-Adjust Value
If this bit is set, CH0DATA and CH1DATA are left-adjusted.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3 – EVSEL[3]: DAC Event Selection bit 3
Setting this bit to one enables event channel EVSEL[2:0]+1 as trigger source for DAC Channel
1. When this bit is 0 the same event channel is used as trigger source for both DAC channels.
• Bit 2:0 – EVSEL[2:0]: DAC Event Channel Input Selection
These bits select which Event System channel is used for triggering a DAC conversion.
29-3
Table 29-3.
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x03
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
shows the available selections.
EVSEL[2:0]
000
001
010
011
100
101
110
111
R
R
7
–
0
7
–
0
DAC Event input Selection
R
R
6
–
0
6
–
0
Group Configuration
R
R
5
–
0
5
–
0
0
1
2
3
4
5
6
7
R
R
4
–
0
4
–
0
Description
Event channel 0 as input to DAC
Event channel 1 as input to DAC
Event channel 2 as input to DAC
Event channel 3 as input to DAC
Event channel 4 as input to DAC
Event channel 5 as input to DAC
Event channel 6 as input to DAC
Event channel 7 as input to DAC
R/W
Atmel AVR XMEGA AU
R
3
0
3
–
0
R/W
R
2
0
2
–
0
EVSEL[3:0]
CH1DRE
R/W
R/W
1
0
1
0
CH0DRE
R/W
R/W
0
0
0
0
EVCTRL
STATUS
Table
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