ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 273

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.9.3
8331A–AVR–07/11
CTRLC - TWI Master Control Register C
Table 21-3.
• Bit 1
When quick command is enabled, the corresponding interrupt flag is set immediately after the
slave acknowledges the address (read or write interrupt). At this point, software can issue either
a STOP or a repeated START condition.
• Bit 0
Setting this bit enables smart mode. When smart mode is enabled, the acknowledge action, as
set by the ACKACT bit in the CTRLC register, is sent immediately after reading the DATA
register.
• Bits 7:3
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2
This bit defines the master's acknowledge behavior in master read mode. The acknowledge
action is executed when a command is written to the CMD bits. If SMEN in the CTRLB register is
set, the acknowledge action is performed when the DATA register is read.
Table 21-4
Table 21-4.
• Bit 1:0
Writing the command (CMD) bits triggers a master operation as defined by
CMD bits are strobe bits, and always read as zero. The acknowledge action is only valid in mas-
ter read mode (R). In master write mode (W), a command will only result in a repeated START or
Bit
+0x02
Read/Write
Initial Value
TIMEOUT[1:0]
–
–
–
00
01
10
11
- SMEN: Smart Mode Enable
ACKACT
–
QCEN: Quick Command Enable
ACKACT: Acknowledge Action
–
lists the acknowledge actions.
CMD[1:0]: Command
Reserved
0
1
7
–
R
0
TWI master inactive bus timeout settings.
ACKACT bit description.
Group Configuration
R
6
–
0
DISABLED
100US
200US
50US
Action
Send ACK
Send NACK
R
5
–
0
R
4
–
0
Description
Disabled, normally used for I
100µs
200µs
50µs, normally used for SMBus at 100kHz
Atmel AVR XMEGA AU
R
3
–
0
ACKACT
R/W
2
0
R/W
2
1
0
C
CMD[1:0]
Table
R/W
0
0
21-5. The
CTRLC
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