ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet - Page 403

• Manufacturer Part Number: ATxmega256A3BU
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3BU

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

31. IEEE 1149.1 JTAG Boundary Scan Interface
31.1
31.2
31.3
8331A–AVR–07/11
Features
Overview
TAP - Test Access Port
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The JTAG interface is mainly intended for testing PCBs by using the JTAG boundary scan capa-
bility. Secondary, the JTAG interface is used to access the Program and Debug Interface (PDI)
in its optional JTAG mode.
The boundary scan chain has the capability of driving and observing the logic levels on I/O pins.
At the system level, all microcontroller or board components having JTAG capabilities are con-
nected serially by the TDI/TDO signals to form a long shift register. An external controller sets up
the devices to drive values at their output pins, and observes the input values received from
other devices. The controller compares the received data with the expected result. In this way,
boundary scan method provides a mechanism for testing the interconnections and integrity of
components on printed circuit boards by using only the four test access port (TAP) signals.
The IEEE Std. 1149.1-2001 defined mandatory JTAG instructions, IDCODE, BYPASS, SAM-
PLE/ PRELOAD, and EXTEST, together with the optional CLAMP and HIGHZ instructions can
be used for testing the printed circuit board. Alternatively, the HIGHZ instruction can be used to
place all I/O pins in an inactive drive state, while bypassing the boundary scan register chain of
the chip.
The AVR-specific PDICOM instruction makes it possible to use the PDI data register as an inter-
face for accessing the PDI for programming and debugging. This provides an alternative way to
access internal programming and debugging resources by using the JTAG interface. For more
details on PDI, programming, and on-chip debugging, refer to
page
The JTAGEN fuse must be programmed and the JTAGD bit in the MCUCR register must be
cleared to enable the JTAG interface and TAP. See
Byte4” on page
When using the JTAG interface for boundary scan, the JTAG TCK clock frequency can be
higher than the internal device frequency. A system clock in the device is not required for bound-
ary scan.
The JTAG interface requires and uses four device I/O pins. In JTAG terminology, these pins
constitute the test access port,or TAP. These pins are:
• TMS: Test mode select. The pin is used for navigating through the TAP-controller state
• TCK: Test clock. This is the JTAG clock signal, and all operation is synchronous to TCK
JTAG (IEEE Std. 1149.1-2001 compliant) interface
Boundary scan capabilities according to the JTAG standard
Full scan of all I/O pins
Supports the mandatory SAMPLE, IDCODE, PRELOAD, EXTEST, and BYPASS instructions
Supports the optional HIGHZ and CLAMP instructions
Supports the AVR-specific PDICOM instruction for accessing the PDI
machine
410.
31, and
”MCUCR – MCU Control Register” on page 47
Atmel AVR XMEGA AU
”FUSEBYTE4 – Nonolatile Memory Fuse
”Program and Debug Interface” on
for more details.
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